1. Field of Invention
The present invention relates to an integrated circuit packaging structure. More particularly, the present invention relates to a packaging structure for a ball grid array that has a small and stable electrical inductance, a small power swing range and ground bouncing, and a capacity to accommodate more power vias.
2. Description of Related Art
Ball grid array (BGA) is a new type of high-pin-count integrated circuit (IC) package, which is an ideal packaging approach for housing ultra-large scale integration (ULSI) chip fabricated using deep sub-micron technology. Due to increasing functional complexity of integrated circuits, the number of transistor units in any single chip increases rapidly. Hence, conventional quad flat pack (QFP) or pin-grid array (PGA) is no longer able to meet the demands for connectivity. For example, QFP or PGA provides at most a hundred to two hundred IC pins, which is barely enough for connecting any slightly complicated digital logic electronic circuits with external devices.
In general, for a personal computer having a conventional 64-bit microprocessor, the core logic circuit must connect with the microprocessor, system main memories such as dynamic random access memory (DRAM) and cache memory such as static random access memory (SRAM) using a full 64-bit wide bus. Consequently, if the core logic is fabricated on a single IC chip, various data buses and corresponding address buses together already demands close to two hundred pins. Since additional control signal lines must also be provided, more than three hundred pins are often required. Currently, BGA is one of the major types of IC packaging that is able to provide for such a high pin count.
A ball grid array package is based on a substrate made from a small printed circuit board (PCB). Any ordinary person familiar with the fabrication technique may know that the packaging process involves the transference of a die by a pick-and-place machine to the surface of the substrate. Thereafter, a wire-bonding machine electrically connects the bonding pads on the circuit chip with bonding pads on the ball grid array printed circuit board using metallic wires. The entire circuit chip including the bonding wires and bonding pads is sealed by plastic in a mold injection operation. Finally, after the plastic is hardened, hundreds of solder balls are attached to the back of the substrate by conducting a solder reflow operation.
In brief, due to the complicated logic functions provided by most ICs and the high operating frequency, IC packages must provide a sufficiently large number of input/output (I/O) pads and overall length of die-to-lead wiring connections must be the smallest possible. In recent years, BGA has become one of the mainstream techniques for packaging highly integrated ICs. Major advantages of BGA packaging includes:
(1) The package can provide a large number of input/output pads.
(2) The package has relatively small external dimensions and hence is particularly suitable for use inside small portable devices such as a notebook computer.
(3) Lead line induction inside the package is relatively small. Hence, ICs may operate at relatively high frequency. Moreover, ground bounce is greatly reduced.
(4) Reflow between solder balls and the PCB rather than the insertion of lead pins into socket holes prevents bending or offset of lead pins during transportation.
FIG. 1 is a schematic top view showing the structural layout of a conventional ball grid array package. As shown in FIG. 1, the front side of the substrate 170 has a central region 180 for attaching a die. Surrounding the central region 180 are a first inner power ring 110, a second inner power ring 120, a third inner power ring 130, a fourth inner power ring 140, a fifth inner power ring 150 and an outer power ring 160. The various inner power rings (110, 120, 130, 140 and 150) and the outer power ring 160 all have different widths. The narrowest region among the inner power rings has a width of about 279 xcexcm while the narrowest region in the outer power ring has a width of about 206 xcexcm. With such a power ring layout, non-uniform inductive effects may be produced when power is supplied to various power rings. Ultimately, a large power swing range is produced and the number of vias (or, through holes) is reduced leading to unstable power transmission and production of deviant electrical characteristics.
Accordingly, one object of the present invention is to provide a packaging structure for a ball grid array that has a small and stable electrical inductance, a small power swing range and ground bouncing and a capacity to accommodate more power vias. Hence, the stability of the power ring transmission source is increased and basic electrical properties of the packages are improved.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a packaging structure for sealing up a silicon chip inside a ball grid array package. The packaging structure comprises of a substrate, a plurality of interface power balls and a plurality of core power balls.
The substrate at least includes a back wiring layer and a front wiring layer. The front wiring layer has a central region, a plurality of inner power rings and an outer power ring while the silicon chip is attached to the central region. Various inner power rings are connected to the silicon chip electrically and the inner power rings are formed next to each other surrounding the central region. Each inner power ring has a substantially identical width and a plurality of vias within the inner power ring and each inner power ring has a different interface voltage. Similarly, the outer power ring connects electrically with the silicon chip and has a substantially uniform width. The outer power ring is close to the inner power rings and encloses all the inner power rings. In addition, the outer power ring has a plurality of vias within the outer power ring and a core voltage Vcore is applied to the outer power ring.
The interface power balls are attached to the back wiring layer and subdivided into a plurality of groups associated with inner power balls, while each group of inner power balls corresponds to one of the inner power rings. Each inner power ball is connected to the corresponding inner power ring through a via so that a proper interface voltage may apply to each inner power ring through the inner power ball. Similarly, the core power balls are attached to the back wiring layer. The core power balls surround the interface power balls and connect with the outer power ring through vias so that a proper core voltage may be applied to the outer power ring.
In one embodiment of this invention, the outer power ring vias are located on one side of the outer power ring further away from the central region. Similarly, the inner power ring vias of each inner power ring are located on one side of the inner power ring further away from the central region. The package structure of this invention further includes a number of metallic wires for connecting the inner power ring with the silicon chip. Pads for bonding metallic wires to the silicon chip are located on the side of the inner power ring closer to the central region. Metallic wires are also used for connecting the outer power ring with the silicon chip. Similarly, pads for bonding metallic wires to the silicon chip are located on the side of the outer power ring closer to the central region.
Since the widths of various inner power rings and that of the outer power ring on the substrate are widened in addition to having an identical dimension, electrical inductance is lowered at the same time. The lowering of electrical inductance leads to a reduction in power swing range and ground bouncing, and an increase in the number of vias can be accommodated by the substrate. Consequently, power transmission quality and stability of the ball grid array package all improve.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.